The 2024 3D InCites Yearbook

Five Workflows for Tackling Heterogeneous Integration of Chiplets for 2.5D/3D Continued from page 27

The Year in Test Continued from page 39

At IEEE ITC in October 2023, Cariad (the electronics arm of Volkswagen) pointed out that testing for ADAS L4 and L5 environments generates a lot of data that, at present, is a missed opportunity for analysis/action. The unification of ATE tests would eliminate the overlap and duplication that come from how test was historically done, with batteries of tests from silos of R&D, quality assurance, security, and product/test/design organizations. Can We Eliminate Silent Data Corruptions? All these advances in testing and unification are nice – but why are very subtle, silent data corruptions (SDC) still happening in the field? Is the answer more testing? They are silent and even if the mechanism is discovered, then additional testing adds expense. At IEEE ITC 2023, there was an excellent panel discussion on SDC about how to catch them in manufacturing, do advanced defect models, improve screening, and the benefits of telemetry. Overall, two main causes were highlighted: Good old-fashioned random points defects and more systemic parametric type failures within complex designs. The point defects can be time zero test escapes or defects that just require a little bit of ‘activation’ time to emerge. Can more “intelligent” high voltage tests be invoked? The more sinister examples, although

parametric in nature, involve very small delay effects and/ or voltage droops under complex power schemes and situations. It begs the question – can more be done in design/validation to cover proper IC workloads? More specifically, if a part is said to be “pass” or “fail”, then the entire condition set needs to be understood ie: at what frequency at what voltage? A multi-layer approach is needed. Should quiescent current testing/fingerprinting be brought back? But after all these efforts – will we merely find the easy mechanisms and the hard ones will continue to elude us? In summary, the industry drivers, such as automotive, compute, and advanced process/package nodes; combined with the never-ending quest to be smaller, better, faster, and cheaper – continue to result in new test challenges. More “shift left” is needed in test to speed up and improve the quality of development. Standards such as IEEE 1838 and UCIe 1.1 are steps in the right direction. Greater unification is happening across the test process flow, including linking SLT and ATE test more closely, and moving more 'on the fly' analytics to the tester for real-time reaction. Lastly, SDC is on the rise and is very hard to solve in a cost- effective manner. 1. “SiC MOSFET Challenges, Demand and Industrialization of Test & Burn-in” – Mark Berry, 3D InCites, 2. “Update on UCIe” – Mark Berry, 3D InCites, October 2022November 2022

level for probe pad access and test IO—similar to planning requirements for high-speed IOs. As well, it is imperative to understand that test considerations cannot wait until the end of the design flow and must also be incorporated into early planning. Packaging engineers must collaborate with test engineers to develop the test IO plan and support static timing analysis and timing simulation requirements. Multi-Domain Co-Design Unlocks the Benefits of HI Successful delivery of heterogeneously integrated systems requires integrated, multi-domain workflows and collaborative design methods throughout the entire design lifecycle. Heterogeneous design generates a tremendous amount of multi-domain data spanning the entire product lifecycle. This necessitates managing a design database for the system, RTL, silicon, and even mechanical design. HI design also includes a broad spectrum of IP, materials, and design kits. All this data needs to be carefully managed and synchronized to ensure efficiency and design integrity throughout the design process. There are numerous advantages and benefits of heterogeneous integration. It enables larger, more complex systems than monolithic SoCs and offers improved power, performance, area, and form factors. However, these benefits do not come for free. There are key challenges that must be met, including optimal decomposition and architecture selection, power delivery through the system, as well as thermal management, timing, and test. Companies that want to overcome the challenges and reap the full benefits of HI design should focus their efforts on building, qualifying, and deploying the five workflows presented in this article.

This intensive level of analysis requires detailed thermal chip models. The models need to account for power density and transistor level heating at the die level, and assuming uniform temperature across the die is no longer realistic. Mechanical stress can also be an issue given the substrate size and different materials used. For example, with a large, multi-reticle silicon interposer sitting on an organic package substrate, the analysis must account for different coefficients of thermal expansion values and must evaluate effects like thermally induced bump stress or substrate warpage. Design for manufacturing and electrical rule checks also need to be performed at both the chiplet and SiP levels. These include checks for electromigration, electrostatic discharge, latch-up, and electrical over-stress. To expedite this type of SiP analysis, the required chiplet models and performance data should be included in their respective design kits. Test Planning and Validation Perhaps one of the more challenging workflows for HI is manufacturing test, as it requires design for test (DFT) infrastructure, wafer-level test, die test in package, and interface testing between the dies. The good news is that there are established DFT standards for testing 2.5D and 3D designs, including IEEE standards 1838, 1687, and 1149.1. Additionally, this workflow is supported by recent DFT advancements like memory testing and built-in self-test (MBIST) with 1838 compliant test access ports; scan testing that supports a 3D package pattern retargeting flow; and die-to-die interconnect testing using differential wearing scheme chains composed of wrapper cells. These methods must be designed early to support SiP testing; this requires planning at the package

Balancing Precision and Throughput in 3D Structures with Advanced Packaging and Motion Control Continued from page 43

These new developments in the motion control space are permitting manufacturers to meet and exceed these strict precision requirements, whilst still maintaining a more than satisfactory throughput, and cost of ownership. The semiconductor industry will continue to innovate beyond the apparent physical limits of silicon transistor production and manufacture devices at the system level that deliver superior performance coupled with power efficiency, all within a standard package footprint or perhaps extending module package sizes. Power and heat dissipation from these complex multi- chip systems will continue to challenge the industry as compute demand continues to scale in high-speed AI applications.

The metrology frame concept also reduces any vibration feedback loop within the system that acts on the tool point, thus minimizing disturbance in the desired placement, process, or inspection steps. As high throughput target placement capabilities in the sub-50 nm realm emerge for heterogeneous chiplet integration strategies, especially when future hybrid bonding processes as considered, a fully integrated motion system including an active isolation platform, multi- axis stage, advanced motion control electronics, and algorithm architecture becomes necessary. Conclusion The semiconductor industry’s relentless drive towards 3D structures and emerging advanced packaging techniques to drive "More than Moore’s Law” objectives require increasingly more complex, precise, and reliable production processes.

Intern Essay Contributors Continued from page 5

Erwan Amade, author of Navigating the World of Semiconductors: My Journey at Megatech, is a 4th year student intern at Megatech. At the age of 21, he studied Chemical and Process Engineering at Lyon 1 and acquired technical expertise at CEA

Mindy Lok, author of Learning About Strategic Semiconductor Communication: My Internship at Kiterocket is a student intern at Kiterocket, a global PR and marketing agency with extensive experience across the technology and sustainable

Leti in Grenoble with Entegris for an internship. He then joined Hybria to specialize in commercial engineering. He's passionate about technology and business, and his academic career reflects this convergence.

living sectors. She is a senior studying public relations with a minor in digital audiences at Arizona State University. She strives to grow and expand her skills as a strategic communicator and digital marketer within business and technology.

3D InCites Yearbook



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