2024 3D InCites Awards Finalists
LPKF Laser & Electronics SE – Laser-Induced Deep Etching
and reliable through-glass vias (TGVs) and other microstructures using traditional drilling methods. Fabricating high-quality, high-density, and small-diameter TGV patterns in glass, without causing damage or stress, is paramount to realizing optimal device performance, achieving miniaturization, and ensuring cost efficiency and yield. To address this challenge, LPKF Laser and Electronics developed its Laser-induced deep etching (LIDE) technology. Using a non-ablative, single-pulse laser- based process, it's possible to achieve high aspect ratio, high-density TGV arrays without stress or microcracks. LIDE is ultra-fast and can create multiple structures in one step. It's also compatible with a range of glass types, including thin and ultra-thin substrates. LIDE technology is said to be highly scalable and suitable for mass production. Its promise of rapidly and reliably producing high-quality glass microstructures positions LPKF as a key enabler in the commercialization and manufacturing of next-generation HI, 3DHI, and chiplet- based devices. decision-making with low power and low latency, promising breakthroughs in chips-first and chips-last packaging and on-wafer extended integration. Multibeam's technology accelerates time-to-market for multi-die packages and overcomes throughput limitations. Its scalable modular architecture allows for seamless transitions from pilot to production. Its adaptable and extendable patterning capabilities and the ability to customize substrates and implement design changes without masks position this technology to drive advancements in silicon integration for future generations.
Technology Enablement Awards DECA The semiconductor industry is transitioning from
Glass substrates are becoming a viable alternative to silicon for HI, 3DHI, and chiplets. However, there are challenges with cost-effectively achieving precise Roman Ostholt, Managing Director of the Electronics business unit at LPKF, discusses the different building blocks (TGV’s, blind vias, cavities, through cuttings) that we can manufacture with the LIDE technology and how to combine them for a advanced packaging application. Multibeam Corporation The semiconductor industry faces a challenge as chip- to-chip interconnect scaling lags behind on-chip scaling, creating a bottleneck in system performance. Advanced packaging's role in improving system performance is hindered by limitations such as beachfront I/O density, die integration issues, and difficulties in achieving high- bandwidth chip-to-chip interconnects, mainly due to variations in chip thickness and die placement accuracy. Patterning system constraints compound these challenges, affecting multi-die integration. The slow cycle times of mask-based lithography technologies contribute to development delays in the Heterogeneous Integration Roadmap (HIR). Multibeam addresses these issues with its Multi-Column E-beam lithography (MEBL) solution. This
silicon interposers to molded fan-out interposers with embedded bridge die for progressively larger devices. As highlighted in TSMC's keynote at IMAPS San Diego in October '23, precisely aligning embedded bridge dies presents a substantial manufacturing challenge that leads to potential risk of yield loss, particularly as devices become more intricate. In response to this manufacturing challenge, DECA has unveiled a groundbreaking solution known as Adaptive Pad Stacks. This innovation signifies a significant leap forward, delivering an order-of-magnitude increase in the allowable die shift for embedded bridge die in molded fan-out interposers. The resulting enhancement in manufacturing tolerance not only safeguards against yield losses but also facilitates the highest density interconnect on more complex devices, including cutting-edge AI processor applications. When integrated ERS Electronic GmbH Wafer and package warpages pose a significant challenge for the widespread adoption of HI, 3D HI, and Chiplet-based architectures. Thermal mismatch among different materials exacerbates this issue, potentially leading to misalignment of interconnects, reduced bonding efficiency, and long-term reliability concerns. Even minimal warpages in these advanced architectures can result in signal integrity issues and degraded performance. Addressing this challenge requires
with proven technologies such as Adaptive Alignment, Adaptive Routing, and Adaptive Metal Fill, Adaptive Pad Stacks provides a robust and comprehensive solution for foundries, OSATs, IDMs, and other industry players involved in designing and producing the most advanced HI chiplet assemblies of the future. Adaptive Pad Stacks™ increase manufacturing process windows by 10X, facilitating the highest density interconnect for more complex devices, including cutting-edge AI processor applications. (CTE), underfill materials, process optimization, and advanced metrology tools for real-time monitoring during manufacturing. To address wafer and package warpage, ERS Electronic GmbH developed the Warpage Measurement System Wave3000. This in-line metrology system accurately measures wafer warpage using advanced optical sensors, identifying risks before proceeding to subsequent processing steps. The Wave3000 can be integrated at various points in the manufacturing line, ensuring continuous monitoring and mitigation, to address warpage caused by integrating multiple materials with varying CTE. With its data-driven approach, the system provides crucial information ahead of time, enabling dynamic adjustments to process parameters and preventing the risk of sending warped wafers that subsequent machines may struggle to handle, ensuring mass production and commercial viability of HI, 3DHI, and Chiplets.
maskless technology enhances multi- die integration with a large write field, high DoF, ultra-fine resolution, and adaptable writing, supporting diverse components on a single substrate for AI applications. MEBL makes it possible to pattern more than 10X larger than current interposers, facilitating wafer- scale integration for processors like HPC, GPUs, and AI engines. With more than 100X DoF improvement over optical lithography, it enables advanced 3D structures and high-resolution interconnects, resulting in a 10x-100x increase in chip-to-chip interconnect bandwidth. This technology expedites in-package data analysis, inference, and
multidisciplinary efforts in material engineering, including substrates with low coefficient
of thermal expansion
The World’s First High Productivity E-Beam Litho Systems–capable of 3D litho, adaptable patterning, and full-wafer deep sub-micron patterning.
The ERS Wave3000, is a specialized warpage measurement system that is seamlessly integrated into various manufacturing line steps.
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