The 2024 3D InCites Yearbook

Five Workflows for Tackling Heterogeneous Integration of Chiplets for 2.5D/3D Kevin Rinebold, Siemens EDA

analysis of SiP signal and power integrity, static and dynamic IR drop, electromigration, and timing. Traditional signal integrity techniques can be used to simulate the high- speed interfaces. Static timing analysis is required for the low-speed signals and the test and control type connections. The power integrity approach taken must be adapted to account for multi-chiplet scenarios. These structures require detailed parasitic extraction that supports both silicon and organic substrates as well as combined SiP and die level extraction for IR drop and electromagnetic analysis. Reliability Analysis Two key areas that require extensive reliability analysis are thermal and mechanical stress. Given the proximity of devices in HI designs, there’s a high likelihood of some type of chip-to-chip or chip-to-package interaction. Therefore, thermal coupling can be a big concern.

planning, IO planning, power delivery, substrate route feasibility, and netlist optimization, along with the corresponding checks, such as LVS and LEC. Predictive modeling is used during floorplanning and implementation to continuously qualify the design, which ultimately streamlines the design process. As detailed design structures, like power planes, get implemented, the modeling fidelity and quality of results will improve. As co-design of one or more custom chiplets is fundamental, tight collaboration between the silicon and package design teams must be fully supported. This means establishing robust multi-domain design data management along with comprehensive engineering change order support to facilitate the exchange of data between teams and disciplines. Design Analysis

These high-speed interfaces can be captured using a library of generic connectivity IP models and then mapped to alternate vendor- specific and technology-specific connectivity IPs. This enables the system designer to assess the power, performance, area, and cost attributes of various scenarios against the system requirements. In this way, predictive modeling helps engineers to hone in on the optimal micro-architecture through the identification of a finite set of scenarios, or micro-architectures, and the exploration of multiple configurations, and partitioning scenarios. Physical Design Planning and Analysis Once an optimal SiP architecture is identified, detailed design can begin, including physical planning, implementation, and analysis. The physical design planning and analysis workflow applies to both interposers and package substrates. It encompasses package floor

In-design modeling further qualifies a design as more content and details become available during implementation. The objective is to identify and resolve issues while corrective action is still relatively easy and inexpensive. These issues are typically related to power, thermal, signal integrity, process rules, or even mechanical integration. The last step is the final signoff of the completed design before release to manufacturing. Because HI designs include a wide range of multi-domain design content and IP, comprehensive data management support throughout all five workflows is required. Now let’s look at the five workflows themselves in a little more detail. Architectural Planning and Analysis The architectural planning and analysis workflow enables system and RTL designers to rapidly explore and capture viable design architectures leveraging three key inputs: • The chiplet components and corresponding design kits • Standard high-speed protocols for internal die-to-die interfaces within the package • External chip-to-chip interfaces between the SiP package and other chips within the system at the PCB level

Figure 1: Chiplets answer semiconductor scaling challenges.

1. Architectural planning and analysis 2. Physical design planning and analysis 3. Design analysis 4. Reliability analysis 5. Test planning and validation As a design moves through the five workflows, it also undergoes modeling and analysis to continuously qualify that the design meets its performance specifications. Predictive modeling is applied during the architectural and physical design planning phases, with the primary goal of qualifying engineering decisions and gaining insight into downstream performance. This also enables team members to validate their packaging and system architecture selection to best address the problems they are trying to solve.

Keeping pace with Moore’s law continues to be challenging and is driving the adoption of innovative packaging technologies that support continued system scaling while doing so at lower costs than comparable monolithic devices. These packaging technologies disaggregate what would typically be a homogenous, monolithic device — like an ASIC or system-on-chip (SoC) — into discrete, unpackaged dies, known as chiplets, specifically designed and optimized for operation within a package in conjunction with other chiplets (Figure 1). This is also referred to as heterogeneous integration (HI), where multiple dies or chiplets are integrated into a system- in-package (SiP) design. Heterogeneously integrated SiP devices offer considerable benefits, including higher performance, lower power usage, smaller area, lower cost, and faster time to market. However, thus far they are designed and produced by only a small number of advanced users. Broad industry proliferation will require a standardization of chiplet models and die-to-die connectivity IP—efforts currently underway— supported by new workflows. This article will focus on five workflows that are essential for planning, implementing, verifying, and co-designing heterogeneous designs (Figure 2).

The design analysis workflow incorporates extraction and simulation tools that support

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Figure 2. Heterogeneous integration workflows.

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