The Year in Test By Mark Berry, COT-NPI Group LLC Is test non-value added? Certainly, some aspects are unchanging. Test is one of the three means to guarantee parts in addition to characterization and the design itself. Given the market backdrop – across automotive, computing, and advanced packaging – new test challenges and value adds have emerged.
we have implemented numerous energy-saving measures as well as expanded green energy production on-site. Currently, we have more than 4,850 m2 of roof area covered with photovoltaic panels, producing approximately 1.5 MW of power, with further expansions planned. Since 2020, the percentage of energy produced onsite with solar power versus our total energy production has increased by more than 4X. At the same time, the number of electric cars in our company fleet has increased by nearly 6X. In addition, our carbon efficiency ratio (the percentage of CO2-neutral and renewable energy versus total energy consumption is nearly 75 percent. These are just some of the numerous green initiatives EVG is implementing to reduce its carbon footprint. We recognize the need to address climate change and we are committed to playing our part. It is truly an exciting time for EVG. 3D and heterogeneous integration have brought fusion and hybrid bonding front and center as critical processes for continuing PPAC scaling. This has fueled tremendous growth within EVG, enabling us to continue to invest in our technology, infrastructure, and people, which in turn helps us to continue to invest in our customers’ success. 2024 will be an amazing year for semiconductor innovation, with further advances in device architectures and packaging integration schemes such as backside power delivery, complementary FET, and 2D materials. Underpinning all these advances is wafer bonding, and as the market and technology leader in wafer bonding, EVG will be by our customers’ side as they march forward on their roadmaps with smaller, faster, more power-efficient, and lower cost-of-ownership products.
challenges especially when using logic from various process nodes. One example is new physical stress mechanisms and a higher probability of interconnect failures. The IEEE 1838 specification for die-to-die stacks is another example of a "shift left" in bringing design and
40 Years of Industry Firsts at EV Group EVG’s strong investments in its products and solutions have led to many industry firsts over the years such as: • The world’s first double-side mask aligner with bottom-side microscopes, which enabled the widespread commercialization of MEMS products, in 1985 • The first production wafer bonding system for volume MEMS manufacturing in 1992 • Installation of the first production bonders for silicon-on-insulator (SOI) wafers in 1994 • Introduction of the patented SmartView ® face-to-face wafer alignment technology in 1999, which revolutionized wafer-level packaging and 3D interconnects • The industry’s first integrated production wafer bonding system launched under the name GEMINI ® in 2000 • The first temporary wafer bonding and debonding systems for ultra- thin wafers were introduced in 2001 • The GEMINI FB fusion bonding system, launched in 2009, enabled the production of the first backside illuminated CMOS image sensors as well as other 3D-IC stacked devices • Launch of SmartNIL large-area nanoimprint lithography (NIL) technology, revolutionizing the high-volume production of optical devices, including AR waveguides and optical sensors, as well as medical and bioMEMS devices in 2014 • BONDSCALE ™ , our next-generation fusion wafer bonder for "More Moore" scaling and front-end processing to address future logic transistor scaling and 3D integration challenges outlined in the IRDS Roadmap, introduced in December 2018 • The LITHOSCALE ® maskless exposure lithography system unveiled in September 2020, which brings the benefits of digital lithography in high-volume manufacturing to a wide range of applications and markets, including advanced packaging • EVG ® 850 NanoCleave ™ layer release system, introduced in 2023, enables nanometer-precision release of bonded, deposited, and grown layers from silicon carriers using an IR laser – thereby eliminating glass substrates for advanced packaging and enabling thin-layer 3D stacking
Three main themes are “shift left”, which is the need for more concurrent development with ever-increasing dependencies between design, packaging, test, and field operation; greater unification in development, production, and across the end-to-end test flow; and the continued war on silent data corruption (SDC) – balanced with test
test closer. KGx starts with the architecture and product planning, needs to be supported by the design, and is delivered by test and assembly operations. More complex test flows and more expensive bill-of- material (BoMs) require greater unification across the end-to-end test flow for development and action in production. Automated test equipment (ATE) and system-level test (SLT) linkage shows a huge increase in the need for SLT after ATE test. SLT can be as much as 50-100x less expensive than ATE, but it historically has been an “island” running very different and long (think 20 minutes) algorithms reflective of end customer use cases. Intel notes that many of its customers run SLT for much longer periods than the company does. Many advances by Teradyne and Advantest facilitate more feed-forward and feedback of test patterns from the two environments to make initial test development results in improved reaction times to enhance upstream ATE test when new failure modes appear at SLT. Other examples include doing more analytics on the tester on the fly. The benefits of this include adaptive tests. For example, if a given batch of material (wafers, finished goods) is exhibiting certain parametric around process corners (fast/slow transistors, high/low power) then the test program can be adaptively and dynamically varied. ATE makers have placed more of these tools within the tester for real-time decision-making, as opposed to a central test floor computer.
economics (Figure 1). What is Shift Left?
The term “Shift Left” has been used increasingly within development to indicate tasks that were once performed sequentially but must now be done concurrently. This is usually due to tightening dependencies between tasks. Several types of “design for…” approaches are taking hold as tools within a broader design for test (DFT) umbrella: S (stress), R (reliability), I (inspection), and O (observability). Beyond test, some automotive firms are using S (security) and S (safety). In simpler products wafer probe was an acceptable means for determining Known Good Die (KGD) as a gross screen before assembly. Now there is far too much value in an 8 FET SiC module [1] or 2.5/3D compute multichip modules such as system-in-package (SiP) and chiplets. The probe must produce as close to KGD as possible. With many forms of advanced packaging, all the interconnects must be checked regardless of accessibility – hence the term known good stack (KGS) and overall known good system (KGS). The Universal Chiplet Interconnect Express (UCIe) specification [2], aimed at die-to-die, has been upgraded to 1.1 addressing more protocols and broader usage models. As 3D die stacking evolves from high-bandwidth memory (HBM) memory to logic, there are new
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3D InCites Yearbook
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