PulseForge, Inc. Fabricating 3D ICs involves stacking thinned silicon (Si) wafers and vertically interconnecting them using through-silicon vias (TSV). To handle thinned Si wafers, temporary bonding to a rigid carrier is required before thinning. The crucial step of wafer debonding, separating the thinned wafer from the carrier, is typically done using chemical solvents, mechanical means, or heating the adhesive. Laser-assisted wafer debonding is an attractive alternative, leveraging optical energy to promote adhesion loss at room temperature. However, challenges like beam width limitations necessitate exploring alternative high-throughput debonding techniques. Photonic Debonding (PDB) utilizes high-intensity light pulses and a proprietary inorganic light-absorbing layer to separate temporarily bonded wafer pairs efficiently. This technology offers a cost-effective alternative to traditional laser techniques, providing benefits such as lower processing costs, minimal thermal impact, reduced mechanical strain, and ash-free debonding. Operating at room temperature, PDB is particularly advantageous for advanced packaging applications, enabling efficient debonding of ultra-thin wafers during back-end-of-line processing with increased final device yield. To bring PDB to market quickly, PulseForge formed strategic partnerships with material suppliers and Siemens DISW The semiconductor industry faces a challenge in adapting to the megatrend of chiplet integration for high-performance computing. Early design planning involves optimizing pin layouts for power, performance, and area, particularly in high pin count ASICs/FPGAs. These are broken down into smaller blocks, forming the complete floor plan over time. Hierarchy in design helps manage complexity by breaking structures into smaller building blocks. Parameterized representation is crucial, especially in die-to-die signal interfaces and power distribution networks within IC packaging.
Terecircuits Current advanced packaging
techniques, such as 3D stacking, HI, and die-on-wafer, introduce complexity and additional process steps, impacting yield and slowing down throughput. To overcome these challenges and unlock the potential of advanced packaging and assembly for complex devices, Terecircuits founders envision their foundational chemistry and processes becoming the industry standard, particularly for semiconductor and display back-end manufacturing.
Components are held securing on a transparent carrier by Terecircuits Terefilm ® photopolymer. A scanning laser cleanly releases components by individual die, row, or column for gentle assembly of small, thin, and fragile assembly without pick & place.
PulseForge PD300SA enables photonic debonding through high-intensi- ty light pulses and proprietary light-absorbing layercoated carriers.
throughput improvement. The applications span from mass transferring MicroLEDs for displays to the non- destructive transfer of delicate materials like Silicon Carbide (SiC), and stress-free assembly of thinned die for 3D stacking and flexible hybrid electronics. Drawing inspiration from the semiconductor industry's success in using light and chemistry for modern integrated circuits, Terecircuits aims to revolutionize the $200 billion assembly and packaging industry, offering a radical solution for assembling individual microscopic components efficiently.
Traditional pick-and-place tools struggle with assembling large numbers of microscopic components, hindering the development of next-gen displays, wearables, and medical devices. Terecircuits addresses this challenge by proposing a shift from slow and inefficient mechanical processes to a fast, controllable chemical approach. Terecircuits’ efficient Laser-Induced Forward Transfer (LIFT) technique, powered by a new photopolymer class, delivers a cost-effective, high-yielding 10-10,000x ZEISS Complexities in 3D HI architectures are slowing down traditional package analysis, impacting success rates and extending development cycles. The limitations of X-ray microscopes (XRM) with field of view (FOV) constraints make fault isolation challenging in large IC packages, resulting in a time-consuming imaging process.
integrators in the temporary bonding/debonding infrastructure. This collaborative approach not only opens new markets and introduces the technology to customers but also validates it and gains support from multiple stakeholders. The company offers a three-tiered approach: a flexible R&D tool for fundamental research, a semi-automated debond tool for limited production, and a fully automated debond tool for fabs as a drop-in replacement for existing equipment. An extensive patent portfolio has also been developed around the equipment and the PDB process. Siemens uses hierarchical device modeling methods to enhance its package prototyping and planning design tool, Xpedition Substrate Integrator (XSI). This innovative set of functions and capabilities facilitates quick and comprehensive updates to design structures consisting of hierarchical building blocks or parameterized pin regions. In contrast to non-graphical IC package floor- planning flows that rely on macro-driven spreadsheets, Siemens' approach minimizes time consumption and reduces the risk of errors during design updates. While non-graphical floor-planning flows can generate an initial draft, keeping up with changes needed for early design analysis
ZEISS revolutionizes 3D X-ray microscopy with AI- powered solutions for non-destructive imaging. DeepRecon Pro enhances imaging in advanced 3D packages, providing superior quality and over 4x faster data acquisition. Meanwhile, DeepScout, also AI- enabled, achieves up to 5x higher resolution for extensive FOV imaging through a deep-learning algorithm.
ZEISS's AI-powered DeepRecon Pro enhances thermocompression bonding (TCB) processes in 2.5 and 3D packages, reducing scan times for assessing alignments and accelerating process development cycles. DeepScout extends high-resolution 3D X-ray imaging benefits to reliability testing, construction analysis, and reverse engineering applications. Congratulations to all our Technology Enablement Award Finalists! After a final round of questions, winners will be selected and announced on February 5, 2024. The 3D InCites Awards Ceremony takes place on March 21, 2024, following the morning keynote session at the IMAPS Device Packaging Conference.
could be more practical. Demonstrating the efficiency of an HBM die-to-die building block with parameterized pin regions, this approach enables quick and efficient package design creation. Notably, effective hierarchy incorporation achieves iterative updates in minutes or seconds. Integrating hierarchical device planning with parameterized pin regions in the xSI design tool offers a revolutionary methodology, significantly
reducing design cycle time to meet performance, power, area, and cost (PPAC) goals.
Xradia 630 Versa and large field of view image of Integrated Fan-out Package reconstructed with ZEISS DeepScout
A design with 4 logic processor chiplets connected to 4 HBM 1.0 memory stacks. The 4 processor chiplets were disaggregated from a monolithic SoC architecture using Hierarchical Device Planning with parameterized pin regions using 4 levels of device hierarchy and are interconnected using UCIe interfaces.
3DInCites.com
3D InCites Yearbook
30
31
Powered by FlippingBook