The “White House of Microelectronics Packaging” Celebrates its 15th Anniversary! Continued from page 33
It proves that the decision to start a leading-edge 3D integration research center 15 years ago was absolutely correct. Today's industry demand for advanced packaging solutions and 3D integration is bigger than ever. The number of microelectronic fabs located in Saxony around Dresden is increasing. Today, Fraunhofer IZM-ASSID focuses on the fabrication of fine metallization structures to reach back-end-of-line (BEOL) structure sizes and develops new interconnect technologies for high-density assembly, wafer, and chip stacking based on various pitches using Cu/Cu hybrid bonding, microbumps for solid-liquid interdiffusion bonding as well as a new type of interconnect— copper nanowire bump. Even if many 3D processes have been similar for 15 years, the devil is in the details. Small changes in the process sequence have an enormous influence on the full flow. The "White House" pilot line allows us to investigate these interactions between different technology steps. Currently, the researchers are seeking new solutions based on chiplets for trusted electronics (Figure 3) and exploring packaging for quantum computing by incorporating new superconductive materials. Moreover, they built a bridge between applied research and academia via a strong scientific cooperation with TU Dresden and established a professorship for nanoelectronics materials in electronic packaging. Now students, Ph.D.s, researchers, and technicians work passionately in a family-like atmosphere of Fraunhofer IZM ASSID.
Figure 3: Assembled chiplet test vehicle with hybrid bonding for trusted electronics (©Photography by Silvia Wolf). The upcoming years will bring rapid growth to the "White House of Microelectronics Packaging". The 3D wafer- level system integration pilot line will be expanded to a 2nd location to extend the 3D technology capabilities. The Center for Advanced CMOS & Heterointegration Saxony was founded with the Fraunhofer IPMS-CNT to bridge the gap for 3D between front-end and back- end wafer-level technology. Among other things, it will accommodate technologies in a 3D bonding hub to support multiple integration schemes for die-to-wafer and wafer-to-wafer system integration. The Center for Heterointegration has been a reality since June 2024! Additionally, with four major European RTO partners (CEA-Leti, IMEC, VTT, and Fraunhofer), a multi-hub test and experimentation facility for edge AI hardware is in the realization phase. The PREVAIL consortium will allow cross-RTO processing in the field of 3D integration for edge AI applications. Once your design for a 3D system is ready, do not hesitate to come over and fabricate it on a 300mm wafer in the beautiful heart of Silicon Saxony at Fraunhofer IZM-ASSID!
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