Cost-effective, High-performance Chips Are Driving the Move to Panel-level Processing Continued from page 9
panel will help improve yield and remove metal contamination and residues that could cause electrical shorts. 3. A panel cleaning tool is needed that can remove flux and contamination from the center of the panel to eliminate void formation and prevent shorts. 4. And finally, a flexible panel handling system is required that can manage thin wafers and panels. ACMR has developed process tools and substrate- handling systems to address these critical PLP process components to drive the future of packaging forward. Summary The transition from WLP to FOPLP reflects the industry’s need for cost-effective, high-performance solutions that
By utilizing fan-out techniques, designs can be made thinner and smaller, which is essential for modern consumer electronics. PLP integration can improve chiplet performance for the massive amounts of data being processed by AI, as well as in other compute-heavy applications. PLP also assists with the implementation of high-bandwidth memory (HBM) to help reduce compute times and power usage. Implementing PLP will also allow for more efficient package device design, as opposed to the more typical board-level packaging approach, which is the direction the industry is heading. Enabling the Transition New process equipment and panel handling is needed to make the transition to PLP. For example:
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1. Electroless and electrolytic plating will be critical in building up the redistribution (RDL), pillar, and bumping layers to create the interconnects needed. 2. Panel bevel etching and cleaning in copper-related processes for both the front and back of the can meet the demands of modern electronics. As technologies evolve and the demand for smaller, more powerful devices increases, ACMR has been working with the industry to develop technology that will help FOPLP play a significant role in the future of semiconductor packaging. US-JOINT Consortium: Strengthening Advanced Packaging Innovation Across Borders Continued from page 27
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We also got the chance to speak with Kulicke & Soffa CTO Bob Chylak about how the collaboration will influence the pace and direction of technology development in semiconductor packaging. “Traditionally, Japanese companies have a leading position for semiconductor packaging materials and substrates and U.S. companies excel at assembly equipment," said Chylak. The marriage of these will allow for the development of complete process flows with access to the latest R&D tools and materials. Combining these with engineering breakthroughs will increase the pace of packaging innovation in the U.S. Beyond the technological advancements, the consortium strengthens ties between Japanese and U.S. companies, reinforcing collaboration in the highly strategic semiconductor sector. With the combined expertise of Kulicke & Soffa, NAMICS, KLA, and other members, the US-JOINT consortium is well-positioned to accelerate breakthroughs in semiconductor packaging and significantly impact the global supply chain.
Chet Lennox, part of KLA’s industry and collaboration team, also shared KLA’s perspective on the consortium’s objectives. “Our main expectation is to work more closely with our partner companies—whether they are material suppliers or other equipment providers—to prove next-generation capabilities in an environment where we can share information freely without concerns over customer IP,” said Lennox. Lennox further elaborated on KLA’s contributions to the consortium detailing what specific industry tools they specialize in and the company's goals to optimize efficiency through collaboration. “We’re contributing a direct imaging lithography tool for patterning wafers and panels,” said Lennox. “One key goal is to co-optimize both the equipment and materials with suppliers, as successful lithography requires both elements to be finely tuned. This collaboration will accelerate our ability to optimize performance and deliver improved solutions to customers.”
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