The “White House of Microelectronics Packaging” Celebrates Its 15th Anniversary! By Juliana Panchenko and Frank Windrich, Fraunhofer IZM-ASSID
connections. While CEA-Leti is primarily researching the material transitions and fundamental mechanisms of bonding, EVG's focus is on optimizing the application and further developing the hardware 9,10 . (Figure 3)
References 1. European Commission, Press Release, “Commission launches Chips Joint Undertaking under the European Chips Act,” November 30, 2023, https://ec.europa.eu/commission/presscorner/detail/ en/ip_23_6167 2. NanoIC, Website, “NanoIC pilot line technologies,” https://www.nanoic-project.eu/en/technologies 3. FAMES, Website, “TECHNOLOGIES,” https://fames- pilot-line.eu/technologies/ 4. The Finnish Chips Competence Center (FICC), Website, “Pilot Lines,” 2024, https://www.ficcc.eu/ pilot-lines 5. Filippo Di Giovanni, Power Electronics World, “Europe approves a project for an advanced chip pilot line in Catania, Italy,” April 15, 2024, https:// www.powerelectronicsnews.com/europe-approves- a-project-for-an-advanced-chip-pilot-line-in-catania- italy/ 6. European Commission, Press Release, “EU invests €65 million in quantum chips,” September 24, 2024, https://digital-strategy.ec.europa.eu/en/news/eu- invests-eu65-million-quantum-chips 7. B. Zhang, et.al., “Scaling Cu/SiCN Wafer-to-Wafer Hybrid Bonding down to 400 nm interconnect pitch”, 10.1109/ECTC51529.2024.00058 8. S. Ghosh, et.al., “EOT Scaling Via 300mm MX2 Dry Transfer - Steps Toward a Manufacturable Process Development and Device Integration”, 10.1109/ VLSITechnologyandCir46783.2024.10631364 9. K. Abadie, et.al, “Vacuum Quality Impact on Covalent Bonding”, 10.1149/MA2023- 02331600mtgabs 10. Q. Lomonaco, et.al., “Stress Engineering in Germanium-Silicon Heterostructure Using Surface Activated Hot Bonding”, 10.1149/MA2022- 02321219mtgabs 11. K. Abadie, et.al. “Study and Control of the Distortion Induced by the Bonding Process for BSPDN Approaches”, 10.1109/IITC61274.2024.10732379 12. Richard van Haren, et.al., “Enabling layer transfer and back-side power delivery network applications by wafer bonding and scanner correction optimizations”, 10.1117/12.2657422 13. Richard van Haren, et.al., “Characterization and mitigation of local wafer deformations introduced by direct wafer-to-wafer bonding”, 10.1117/12.3010477
project was CarrICool leveraging the integration of an active cooled Si interposer with TSVs surrounded by fluidic channels for advanced thermal management in high-performance computing applications (Figure 2).
15 years ago, Fraunhofer established a leading-edge research center for 3D integration and advanced wafer-level packaging on 200/300mm wafer sizes. It was founded based on visionary ideas in the field of microelectronic packaging from the former director of Fraunhofer IZM, Prof. Herbert Reichl. Supported by the Free State of Saxony, the Federal Ministry of Education and Research (BMBF) Germany, the European Commission, and the Fraunhofer Society the Center “All Silicon System Integration Dresden - ASSID” was founded directly in the heart of Silicon Saxony in a fully industry compatible clean room environment (Figure 1).
Figure 3: Robot handling a 300-mm wafer in an EVG system installed at LETI’s cleanroom. ©Andréa Aubert/CEA. Another example among many is the relationship between dielectrics and bond strength. Especially in the area of low bonding temperatures, dielectrics and activation in the bonder play an increasingly important role. A precise understanding of bond strength, adhesion, and adherence, as well as the associated effects and potential defects, is essential to guarantee the highest process yield and bond stability 11 . Particularly within these fundamental research topics, CEA-Leti generates high value. Another important field of research was realized as part of a collaboration between CEA-Leti, ASML, and EVG. The fundamental relationships between bonder-induced overlay data, process-induced distortions, and distortion compensation in the scanner were investigated. Using high-resolution data, bond distortions could be efficiently optimized to meet the compensation possibilities of lithography. In this co-optimization, an overlay of less than 10nm was demonstrated, which is essential for BSPDN and subsequent sequential 3D integration. 12,13 Conclusion Europe is ushering in a new chip renaissance thanks to renewed public focus and investments in its domestic semiconductor industry coupled with Europe’s historical strengths in leading-edge research and key process areas that are fueling semiconductor innovation. Besides funding, increased collaboration between companies and research institutes across Europe is essential to making this renaissance a reality, and we are witnessing many examples of this today. It is truly an exciting time to witness this revival in the making.
Figure. 2: Si interposer wafer with fluidic channels for active cooling (© Photography by Silvia Wolf) The expertise in Cu TSV technology opened up the integration of TSVs in custom ASIC devices by TSV's last 3D integration. Such an integration approach allows leading-edge systems in package (SiPs) for various detector and sensor applications in the medical and industrial fields. To support the industrial demand for small- and mid-size volume pilot line manufacturing, an ISO 9001 quality system was established in 2014. The middle and end of the decade were focused on extending the wafer-level packaging capabilities to address different markets. We focused on technology development for RDL1st fan- out wafer-level packaging with multi-die embedding to build highly miniaturized SiPs. The technology was used to develop a universal sensor platform. Furthermore, the integration of Cu/Cu hybrid bonding technology was investigated at a very early stage in the development. Activities to develop the packaging of a full 300 mm wafer-scale integrated high-performance computing system were also realized. The time is running extremely fast and in semiconductor R&D even faster. Today we see real 3D integration in numerous products driven by the artificial intelligence (AI) and high-performance computing (HPC) market. We see Si interposers in high-volume manufacturing and are in the era of chiplet integration. The industry has wafer- scale computing systems for big data AI applications in the market and we believe that Interconnectology will be the future.
Figure 1: Fraunhofer IZM-ASSID “The White House of Microelectronics Packaging” It was the first 300mm R&D facility for this purpose in Germany. The first three years were dedicated to upgrading the “White House” clean room from a back- end chip-scale packaging facility to a leading-edge 3D integration facility, at a time when the mainstream industry was focusing on chip-scale packaging and embedded wafer-level ball-grid array (eWLB) technology. The focus in the early years of the small, strong, and motivated researcher team was to develop advanced wafer-level packaging technology building blocks in 2.5D / 3D integration. In cooperation with local 300mm foundry partners, through silicon vias (TSV), re-distribution layer (RDL) and micropillar interconnect technologies were developed and transferred to volume production. All required technology building blocks for 2.5D / 3D integration starting from wafer bonding and thinning, multi-layer RDL in Cu damascene and polymer flavor, TSV formation, interconnect fabrication, die assembly, and in-line metrology were set up to form a leading-edge industry-compatible 200/300 mm heterogenous 3D wafer-level system integration pilot line. The past 15 years have brought numerous scientific projects and industrial cooperations with institutions all over the world. The first years were focused strongly on the above-mentioned topics on the development of Cu TSV processes and 2.5D silicon interposer fabrication with flip-chip micropillar interconnects. A key R&D
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