US-JOINT Consortium: Strengthening Advanced Packaging Innovation Across Borders By Avery Gerber
OSATs makes up the bulk of the packaging resources for the semiconductor industry. Most of these facilities are located in the AP region, with China and Taiwan having over half of the OSAT facilities and revenue across the industry. According to IDC, the top 10 OSAT companies are responsible for over 80% of the industry's revenue, with ASE and Amkor, the top 2 OSAT companies, accounting for over 40% market share. The top 10 OSATs are located primarily in Taiwan and China, with one in Singapore. The OSATs have facilities spread throughout the AP region, for example, Amkor has packaging facilities in Taiwan, China, Korea, Japan, Malaysia, Vietnam, and the Philippines. 1. ASE Group: Headquarters Taiwan 2. Amkor: Headquarters U.S., Manufacturing mostly AP 3. Powertech Technology Inc: Headquarters Taiwan 4. Chipmos Technologies: Headquarters Taiwan 5. King Yuan Electronics Co. Ltd: Headquarters Taiwan 6. Formosa Advanced Technologies: Headquarters Taiwan 7. JCET: Headquarters China 8. UTAC Holdings Ltd: Headquarters Singapore 9. Lingsen Precision Industries Ltd: Headquarters Taiwan 10. Tongfu Microelectronics Co.: Headquarters China
Samsung has a considerable 3D packaging effort for its advanced logic foundry partners, Samsung Advanced Logic, and HBM located in Korea. SK Hynix performs most of its HBM packaging and development in Korea as well. All the memory companies are partnering with TSMC, or other OSATs to get their HBM integrated into advanced packages. OSATs are a big part of the 3D ecosystem, an most packaging development happens at these companies. ASE has long partnered with TSMC and got a shout-out at TSMC’s North America OIP presentations. Amkor is also moving forward with TSMC in Arizona for 3D packaging technology. Panel-level packaging (PLP) is a hot new technology for chiplet manufacturing. Wafer-level packaging (WLP) cannot support the volume of chiplet devices needed by the microelectronics industry. The industry is shifting from using wafers or round substrates to glass panels. Innolux in Taiwan is operating a 3.5G panel-level packaging plant. TSMC just purchased a 5.5G flat panel factory for the same purpose and Micron has been looking at several flat panel facilities for PLP. TSMC expects to have a 9-reticle package in production by 2027.
processes; packaging processes are now equally important to achieve the performance required for modern applications. The growing influence of companies like Google, Amazon, and other tech giants in the semiconductor industry highlights the need for a holistic approach that integrates both design and packaging to drive innovation,” Mitsukura added. Ken Araujo, Vice President of Sales and Marketing at NAMICS, emphasized the strategic advantage the US-JOINT consortium provides in introducing next- generation materials for advanced packaging solutions. “This initiative allows us to showcase new materials directly to customers who may have emerging 3D or complex package designs,” Araujo said. “By using the consortium’s resources, we can conduct real-world evaluations rather than relying on simulations. This helps customers understand if materials, such as underfill or liquid compression molding (LCM), are compatible with their designs, while also providing us with immediate feedback.” Araujo also noted that the hands-on collaboration at US-JOINT would not only reduce design cycles but also help NAMICS fine-tune its material development to align with evolving customer needs. “Instead of using test vehicles or purely simulation-based studies, we can build actual products at the consortium. This allows us and our customers to see firsthand if these materials work within their intended packages or if design modifications are required,” Araujo added.
As global semiconductor demand continues to surge, international collaboration has become essential for driving technological innovation. The US-JOINT consortium represents a key initiative in fostering cross-border cooperation between Japan and the United States. This groundbreaking collaboration brings together 10 companies- Azimuth Industrial Co. Inc., KLA Corp., Kulicke & Soffa Industries Inc., TOWA Corp., ULVAC Inc., Moses Lake Industries Inc., MEC Co. Ltd., NAMICS Corp., Tokyo Ohka Kogyo Co. Ltd., and Resonac Corp. to work on advanced semiconductor packaging research and development. Three of these companies— KNS, NAMICS, and KLA —are members of the 3D InCites community. In response to the growing need for sophisticated packaging solutions, the US-JOINT consortium aims to leverage the unique strengths of its participants in both countries. I spoke with several key members, including Kazuyuki Mitsukura, the technical director leading US- JOINT at Resonac America, to learn more about the initiative’s goals. We also spoke with representatives from KLA, Kulicke & Soffa, and NAMICS. “US-JOINT is being established with the participation of 10 companies, including U.S.-based firms,” Mitsukura said. “This program builds on the experience of JOINT2, facilitating collaboration with participants and customers from major semiconductor, fabless, and tech companies. We are setting up US-JOINT in Silicon Valley, where cutting-edge semiconductor designs are born.” He highlighted a paradigm shift in semiconductor development. “It’s no longer just about front-end
Worldwide Top 10 OSAT Companies, 2022 Market Share
Figure 3: Panel level packaging panel dimensions (Source: Innolux) Advanced packaging will continue to be an area of strong growth for the industry. In a recent earnings call, CC Wei, CEO of TSMC, mentioned that in 2023, the foundry business was about $117 billion; however, with the addition of advanced packaging to TSMC’s and other companies' product lines, the foundry business was estimated to be 250 billion dollars. That’s a doubling of the foundry market and is mostly due to advanced packaging. With a market size of over $100 billion and no signs of the AP region slowing down in the packaging market, AP will continue to be the hot spot for advanced packaging for some time to come.
Figure 2: Worldwide Top 10 OSAT companies, 2024 market share. (Source: IDC) With all of the chiplet noise in the marketplace, one might think that most of the chiplet development occurs either at TSMC in Taiwan or at Intel in the U.S. This is far from the case. A considerable amount of chiplet devices are assembled and packaged at the OSATs. AMD has partnered with Tongfu Micro to handle its chiplet packaging. Tongfu and AMD co-developed their chiplet capability in 2017 when AMD first started chiplet development. Intel’s Embedded Multi-die Interconnect Bridge (EMIB) packaging, which is considered 2.5D, is done in Malaysia as well. Foveros is packaged in the U.S. at the moment, but that may also be outsourced to AP.
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