Taking 3D IC Heterogeneous Integration Mainstream By Tony Mastroianni and Todd Burkholder, Siemens EDA Over the last several years, chiplet-based heterogeneous
Exchange (CDX) was established within the Open Compute Project (OCP) to promote and support this technology and eventually deliver it to the mainstream. The CDX group comprises EDA vendors, Fabs, OSATs, and substrate material providers. The charter of the CDX group is to promote a chiplet ecosystem by defining models that are necessary to support the 3D IC design process, as well as the different types of design kits that this requires. Therefore, we set out to establish an ecosystem of design kits to enable 3D IC design throughout the semiconductor industry and address the fact that the packaging community has lacked the well- structured design kits and PDKs available for traditional ASIC technologies. The idea was that we could eventually have reusable chiplets out in the marketplace, and that's what we're promoting in the CDX group. Therefore, it was critical to develop and leverage existing standards for the various 3D IC design kit formats (which we call 3DKs), and we wanted the 3DKs to be in machine-readable formats that can be consumed by the tools and the workflows. In turn, we needed to have the EDA companies support these workflows and the different formats. Finally, to make the critical link to manufacturing, the OSATs—the foundries that generate
package integration has emerged as a promising alternative to traditional monolithic package solutions; the so-called homogenous SoC design. 3D IC heterogeneous integration is a system approach, wherein what typically would be implemented as an SoC is disaggregated into solid, fabricated IP blocks; i.e., chiplets . These chiplets typically provide a specific function implemented in an optimal chip process node. Several chiplets and an optional, custom SoC device can be mounted and interconnected in a single package using high-speed/bandwidth chiplet-to-chiplet interfaces. The resulting 3D IC heterogeneously integrated packages deliver greater performance at a reduced cost, higher yield, and have only a slightly larger area than a traditional monolithic SoC package. This system-oriented approach, known as system technology co-optimization (STCO), differs from traditional IC design. STCO spans five significant activities that are both complex and sophisticated: architectural planning and analysis, functional design and test, physical design planning and verification, and electrical and reliability analysis.
the data for these different design kits—also had to be part of this ecosystem. The 3DKs: 3D IC Design Enablement defined design enablement infrastructure. It includes IP: the reusable building blocks of SoC designs. There are process design kits, which include the technology rules for creating extraction decks, place and route decks, et cetera. There are As mentioned, the IC design process has a very structured, well-
Figure 1: 3D IC heterogeneous integration requires a co-design and co-optimization approach (STCO). With this new approach come many advantages, opening new possibilities in electronic system design; however, the question facing us is how to facilitate the adoption of this exciting yet esoteric 3D IC methodology, one requiring a high degree of expertise and effort. With that quest in mind, in 2021, the Chiplet Design
also macros for memory and analog signal-type designs. We’re trying to extend that concept for many things in the packaging world, but a different set of design kits is required. So, 3D IC design requires a comprehensive set of new design enablement kits to support the design, verification, and handoff to manufacturing. These design enablement kits fall into five key areas, as reflected above. These are physical design, electrical
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