Cost-effective, High-performance Chips Are Driving the Move to Panel-level Processing By Jim Straus, ACM Research
thinkdeca.com
standard 600mm square panels Realizing the full value of
To help resolve packaging supply chain constraints, the packaging industry is moving from round substrates to square panels. Both wafer manufacturers and outsourced assembly and test (OSAT) packaging suppliers have proposed using square glass panels as the substrate for packaging the large-area chiplets. This will significantly increase the number of chips that can be processed on a single panel and should ease current supply constraints. The industry for now has settled on panel sizes of 515mm x 510mm, which has 3x the area of a 300mm silicon wafer; and 600mm x 600mm, which has 5x the area of a 300mm wafer (Figure 1).
600mm x 600mm
Artificial intelligence (AI) is driving the need for faster processing speeds to keep up with the large language models. As a result, we see multi-reticle packages using 2 x 800 mm 2 chips in production in a single package . These larger chip sizes and the need for better yields and higher capacity drive the move from wafers to larger rectangular substrates for the packaging process. The move to fan out panel-level packaging (FOPLP) is partly driven by the industry’s move to packaging chips on a substrate to reduce the limitations and constraints of the wafer-level packaging process. The rapid adoption of multiple-reticle chiplets has created packaging shortages as the FOWLP packaging process is capacity-constrained due to the large size of these packages. To improve the capacity situation, packaging companies are working to develop panel-level packaging (PLP). Instead of using a round wafer in the packaging process, a square substrate will be used for PLP. AMC Research (AMCR) has a long history of success with wafer-level packaging (WLP), and it is supporting the transition to PLP with new approaches for cleaning and deposition technologies. Before we move into some details of PLP, however, let’s discuss why we need to move to larger substrates in the first place. Large-package Design Challenges Building packages that are larger than 2 x 800mm 2 has multiple challenges. One of the biggest issues is how many 800mm 2 chips can be placed on a 300 mm wafer or packaging substrate. With a chip size of ~800mm 2 , about 64 chips can fit on a round 300mm wafer. However, this does not consider yield. The chip is square and the wafer is round, so a significant amount of substrate goes to waste in the chip's processing. This is because a considerable amount of area at the edge is lost due to the mismatch in shape.
515mm x 510mm
Initial format for 300mm test designed to utilize existing industry 300 mm probe capacity
300mm wafer
600mm Figure 1: 300mm wafer compared to 515mm x 510mm and 600mm 2 panels
Advantages of Panel-level Packaging Transitioning to PLP has some advantages over WLP. For example, PLP enables the industry to significantly increase the substrate area for building chiplets, improving yield and lowering packaging costs. The larger area allows more chips to be assembled simultaneously, increasing capacity and thus reducing the current supply constraints. FOPLP will allow for the integration of various die technologies (e.g., logic, memory, and RF) more easily in a single package, which supports more complex system designs.
Current optimized format full 600mm active area for maximum utilization
Continued on page 69
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